1. Field of the Invention
This invention relates to the field of electronic memory systems. In particular, the present invention relates to a system and method for providing high speed interface access to memory resources.
2. Related Art
Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems facilitate increased productivity and cost reduction in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. The electronic systems that provide these advantageous results often rely upon information such as instructions or other data to perform their designated functions. The information is typically stored in an electronically readable medium referred to as a memory. The speed at which various electronic components interact with the memory (such as access information) typically has a significant impact on the performance and capabilities of a system. The integrity of the information delivery also has a significant impact on the performance of the system. However, traditional memory technologies often require expensive configurations and manipulations to provide relatively fast memory access with reliable delivery.
As applications and functionality of electronic systems advanced there is often a requirement for greater information storage capacity. One traditional approach to increasing memory capacity is to utilize peripheral memory mediums that are conducive to storing relatively large quantities of information such as hard drives or memory disks like digital video disks (DVD), CD, etc. While large capacity storage mediums usually provide large storage space, interfacing operations such as reading or writing the information are usually relatively slow. There are traditional system memory components that are faster than the peripheral large capacity storage devices, but the traditional system memory components are usually limited in capacity due to the exorbitant costs associated with producing a single large capacity system memory array. Therefore, in order to achieve requisite capacity without overwhelming expense a plurality of smaller traditional system memory arrays (such as memory chips) are provided. However, dividing the system memory up into a plurality of system memory arrays increases the demands on the system and expands adverse affects while slowing down the system memory access operations.
Traditional system memory architectures typically have several undesirable characteristics such as a relatively high pin count, noisy environment, high Federal Communication Commission (FCC) radiation, and large board area. Traditional interfaces between system controllers and memory arrays (such as a memory chip) typically consist of a plurality of memory chips spread out over a printed circuit board area. The system controller is connected by parallel bus lines to each system memory array within the overall system memory scheme. Each of the bus paths requires an input or output pin with an input/output buffer. Each of the bus paths also has capacative loading and generates detrimental flux that results in noise on a parallel bus path. The noise has the potential to corrupt the interpretation of the parallel signal and adversely impact the integrity and reliability of the information handling capabilities. Given that there are a large number of parallel toggling bus lines, noise becomes a significant problem in a traditional system memory architecture.
The system has to deal with coordinating interface operations between the system and the different memory arrays (e.g., memory chips). The coordinating memory interface operations strains system resources that would otherwise be available to perform other processing activities. The system in a traditional memory architecture has to ensure that the memory addressing configuration appropriately identifies memory locations of all the arrays in a cohesive manner. The system in a traditional memory architecture also has to coordinate signals on control lines to the different memory arrays to provide for cohesive overall memory control. The significant number of parallel bus paths to each memory array dramatically increases the complexity of the system controller memory coordination responsibilities.
FIG. 1 is a block diagram of prior art system memory interface 100 showing a typical way a traditional system interfaces with its traditional memory array. System memory interface 100 consisted of a system controller 110 and a memory chip 120. The system controller 110 is connected to memory chip 120 by a plurality of communication buses each running to a separate memory module (not shown) within memory chip 120. Each memory component within memory chip 120 has 16 data bit ports (read and write lines), 20 address bit ports and a byte (4 bit) enable control ports. For example, there are 8 data bus lines each for data bits 0–7, 8–15, 16–23, 24–31, 32–39 and 40–47 for both transmit (read) and receive (write) for a total of 96 data bus lines. In addition there are 20 address bus lines and control bits 0–3 for a total of 24 bus lines. The data and address bits are provided synchronously upon a clock edge. The receive clock is provided by the system clock and the transmit clock is the same clock after the buffering by the memory chip to meet the setup and hold time requirements at the interface.
What is required is a system and method that facilitates efficient communication of information between a system controller operating at a relatively high speed serial communication rate and a memory array operating at a relatively slow speed serial communication rate.